Years on a coin cell, or self-powered.
Rare events should not require a processor and volatile memory to remain active around the clock.
The enabler of neuromorphic edge AI
Always-on AI for the physical world, at microwatt budget.
Spiketronix designs ultra-low-power neuromorphic AI chips, and the software to run them, built on non-volatile compute-in-memory.
Why edge intelligence must change
Too far for the cloud. Too costly to idle.
Decide in microseconds, on the device.
Local inference removes network delay and reacts while the signal still matters.
Catch the fault before the machine fails.
Continuous local sensing keeps critical data private and surfaces early warning patterns.
Three technologies, one solution
Built around the sparse, temporal nature of the physical world.
Each pillar removes a different source of wasted energy. Together, they make always-on intelligence practical.
Neuromorphic
Sleeps until something changes.
Spiking neurons stay silent until their input changes, then emit a brief spike — no event, no computation, no energy. Time and sequence are built in, so vibration, sound and biosignals are computed the way the brain does.
Event-driven
Temporal
Sparse
Non-volatile FeRAM
Remembers the model with power removed.
Once compute is sparse, the real cost is remembering the model through the long gaps between events. FeRAM holds every weight with the power fully off — so the gaps cost nothing, and the chip is instant-on.
GlobalFoundries 22nm FD-SOI
Zero standby
In-memory compute
Computes where the weights are stored.
A conventional chip shuttles weights to a separate compute unit every operation — and moving data wastes time and energy. Compute-in-memory does the maths where the weights already live, so nothing moves.
Analog in-memory MAC
No weight movement
Massively parallel
A complete platform
From silicon architecture to trained model and deployment.
The platform isn't a bare accelerator block you're left to wire up. Silicon, model and toolchain are co-designed as one system, so it ships as a finished part you can build a product around.
Plug-and-play hardware
Mixed-signal accelerator SoC
The neuromorphic compute engine and memory system integrated as one chip platform.
Standard digital interfaces
Designed to connect with conventional embedded systems and host controllers.
On-chip calibration and control
Device variation is handled inside the platform rather than pushed onto the customer.
Integration-ready platform
A deployable architecture rather than a custom research demonstrator.
Neuromorphic SoC
Ultra-low-power edge AI
Full software stack
Hardware-aware AI training
Models are trained around the actual memory, quantization and compute behaviour.
Configuration SDK and drivers
Standardized configuration and control instead of custom laboratory scripts.
Model deployment toolchain
Moves a trained network into a configured, deployable hardware implementation.
Adaptive behaviour
The deployed model can be calibrated to the device and its operating environment.
- 01Hardware-aware SDKTraining and deployment toolchain.
- 02On-chip controlCalibration and host interface.
- 03Spiking neuron fabricEvent-driven digital neurons.
- 04Mixed-signal front-endSensor input, ADCs and sense amps.
- 05Compute-in-memory crossbarMultiply-accumulate inside the array.
- 06FeRAM technologyNon-volatile ferroelectric devices, the core.
The team behind Spiketronix
Deep expertise across device, system and commercialization.
Alptekin Vardar
Edge-AI hardware and system architecture; PhD from TUM.
CEO & System Architect
[email protected]
Martin Landgraf
Two decades in deep-tech business development and funding.
CFO & Strategy
[email protected]
Thomas Kämpfe
Ferroelectric devices and neuromorphics; professor at TU Braunschweig and team lead at Fraunhofer IPMS.
Scientific Advisor
[email protected]Contact
Get in touch.
We are happy to answer questions and provide more details about Spiketronix. Reach out for collaborations, partnerships or additional information.